Arithmetic core Project Titles

S.NO
PROJECT CODE
NAME OF PROJECT
18
WVA18
Fast Radix-10 Multiplication Using Redundant BCD Codes(IEEE 2015)
17
WVA17
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block(IEEE 2015)
16
WVA16
An Optimized Modified Booth Re-coder for Efficient Design of the Add-Multiply Operator(IEEE 2015)
15
WVA15
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability(IEEE 2015)
14
WVA14
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations(IEEE 2015)
13
WVA13
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its
Application in Digital Signal Processing
12
WVA12
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters
11
WVA11
Design of Fixed-Width Multipliers With Linear Compensation Function
10
WVA10
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
09
WVA09
Reducing the Computation Time in (Short Bit-Width) Two’s Complement Multipliers
08
WVA08
SET D-Flip Flop Design for Portable Applications
07
WVA07
Low-Power and Area-Efficient Carry Select Adder
06
WVA06
Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error
05
WVA05
On Modulo2^n+1 Adder Design
04
WVA04
Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
03
WVA03
Efficient Design of a Hybrid Adder Using Quantum-Dot Cellular Automata
02
WVA02
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers
01
WVA01
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection

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