Digital Signal Processing (DSP) core

S.NO
PROJECT CODE
NAME OF PROJECT
12
WVD12
Efficient FPGA and ASIC Realizations of a DA Based Reconfigurable FIR Filter
11
WVD11
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique
10
WVD10
An Efficient Implementation of Floating Point Multiplier
09
WVD09
Radix-8 Booth Encoded Modulo 2^n-1  Multipliers With Adaptive Delay for High Dynamic Range Residue Number System
08
WVD08
Word-Level Finite Field Multiplier Using Normal Basis
07
WVD07
FFT Implementation with Fused Floating-Point Operations
06
WVD06
High-Speed Architectures for Multiplication Using Reordered Normal Basis
05
WVD05
A Low-Power Single-Phase Clock Multiband Flexible Divider
04
WVD04
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
03
WVD03
Binary Integer Decimal-Based Floating-Point Multiplication
02
WVD02
BPSK System on Spartan 3E FPGA
01
WVD01
Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

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