Low Power Design Project Titles

S.NO
PROJECT CODE
NAME OF PROJECT
14
WVL14
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic(IEEE-2015)
13
WVL13
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree(IEEE-2015)
12
WVL12
Recursive Approach to the Design of a Parallel Self-Timed Adder(IEEE-2015)
11
WVL11
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme(IEEE-2015)
10
WVL10
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator(IEEE-2015)
09
WVL09
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
08
WVL08
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
07
WVL07
Design of Sequential Elements for Low Power Clocking System
06
WVL06
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops
05
WVL05
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
04
WVL04
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
03
WVL03
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique
02
WVL02
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
01
WVL01
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree

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