VLSI CMOS DESIGN 2015 Project List
S.NO |
PROJECT CODE |
NAME OF PROJECT |
00 |
WCV00 |
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating (IEEE 2015) |
01 |
WCV01 |
A 5.8Ghz wideband TSPC Divide-by-16/17 Dual Modulus Prescalar (IEEE 2015) |
02 |
WCV02 |
Logical Effort for CMOS-Based Dual Mode Logic Gates (IEEE 2015) |
03 |
WCV03 |
Design of Testable Reversible Sequential Circuits(IEEE 2015) |
04 |
WCV04 |
Quaternary Logic Lookup Table in Standard CMOS(IEEE - 2015) |
05 |
WCV05 |
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic(IEEE-2013) |
06 |
WCV06 |
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree(IEEE-2013) |
07 |
WCV07 |
Recursive Approach to the Design of a Parallel Self-Timed Adder(IEEE-2015) |
08 |
WCV08 |
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme(IEEE-2015) |
09 |
WCV09 |
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator(IEEE- 2015) |
