Overview:

This certified course is a thorough introduction to the VLSI, Advanced Digital System Design concepts, VHDL and Verilog language for designing digital design modules. The emphasis is on writing solid simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses to simulate the design general and writing testbench for the specified design. The information gained can be applied to any digital design by using a top-down design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the advanced VHDL and verilog topics.

Skills Gained:

After completing this course, you will how to:

• Identify the differences between VHDL and Verilog coding styles
• Write RTL coding for digital system design
• Distinguish coding styles between simulation and testbench
• Use concurrent and procedutral control structure to regulate information flow
• Implement common VHDL/Verilog constructs (Finite State Machines [FSMs], RAM/ROM data structures)…etc
• Write a HDL testbench and identify simulation-only constructs
• Create and manage designs within the mentor graphics tool environment

Syllabus: