Advanced Certified Course in VLSI DESIGN


This certified course is a thorough introduction to the VLSI, Advanced Digital System Design concepts, VHDL and Verilog language for designing digital design modules. The emphasis is on writing solid simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses to simulate the design general and writing testbench for the specified design. The information gained can be applied to any digital design by using a top-down design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the advanced VHDL and verilog topics.

Skills Gained:

After completing this course, you will how to:

  • Identify the differences between VHDL and Verilog coding styles
  • Write RTL coding for digital system design
  • Distinguish coding styles between simulation and testbench
  • Use concurrent and procedutral control structure to regulate information flow
  • Implement common VHDL/Verilog constructs (Finite State Machines [FSMs], RAM/ROM data structures)…etc
  • Write a HDL testbench and identify simulation-only constructs
  • Create and manage designs within the mentor graphics tool environment


1. Introduction to VLSI

  • VLSI Design Flow
  • ASIC vs FPGA
  • RTL Design Methodologies
  • Introduction to ASIC Verification Methodologies
  • Applications of VLSI

2. Advanced Digital System Design

  • Introduction to Digital Electronics
  • ALU circuits
  • Data processing circuits
  • Universal Logic Elements
  • Combinational circuits – Design and Analysis
  • Latches and Flip Flops
  • Shift Registers and Counters
  • Sequential circuits – Design and Analysis
  • Memories and PLD
  • Finite State Machine


  • Introduction to VHDL
  • Applications of VHDL
  • VHDL language concepts
  • VHDL language basics and constructs
  • Levels of abstraction
  • Data types, Enumerated data types
  • VHDL operators
  • Declarations - libraries, entity, architecture
  • Data Objects - signal, variable, constant
  • Dataflow model - Concurrent assignment statements
  • Structural model - Component declarations
  • Component instantiation
  • Generate Statement, Configuration block
  • Behavioral model - Process statement, Sequential statements
  • Delay concept, Generic concept
  • Arrays, Records, Procedures, Functions
  • Memory modeling
  • FSM –structure, moore vs mealy, coding styles, registered outputs
  • Standard packages, Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Advanced VHDL Topics – assertions, attributes, file handling

4. Verilog HDL

  • Introduction to Verilog
  • Applications of Verilog
  • Verilog language constructs
  • Abstraction levels
  • Data types
  • Verilog operators
  • Declarations - module, ports types
  • Nets and Registers
  • Arrays
  • Memory modeling
  • FSM –structure, moore vs mealy, coding styles, registered outputs
  • Gate level design
  • Data flow design – assign statements
  • Structural design
  • Behavioral design – procedural statements, always blocks
  • Initial blocks, begin…end, fork…join, blocking and non-blocking
  • Procedural control statements – if, case, loops
  • Tasks, Functions
  • Testbenchs
  • Advanced topics – system tasks, compiler directives, UDP
  • File input and File output


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