VLSI CMOS DESIGN 2015 Project List

S.NO
PROJECT CODE
NAME OF PROJECT
00
WSV00
Embedded System Design for Digital Control of Single Phase Z-Source Inverter using FPGA (IEEE 2015)
01
WSV01
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line (IEEE 2015)
02
WSV02
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC (IEEE 2015)
03
WSV03
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing (IEEE 2015)
04
WSV04
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority (IEEE 2015)
05
WSV05
Smart Reliable Network-on-Chip (IEEE 2015)
06
WSV06
AHB Compatible DDR SDRAM Controller IP Core for ARM Based SOC (IEEE 2015)
07
WSV07
VLSI Design for SVM-Based Speaker Verification System (IEEE 2015)
08
WSV08
Z-TCAM: An SRAM-based Architecture for TCAM (IEEE 2015)
09
WSV09
32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands (IEEE 2015)
10
WSV00
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic(IEEE 2015)
11
WSV01
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Code(IEEE 2015)
12
WSV02
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m) (IEEE 2015)
13
WSV03
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree(IEEE 2015)
14
WSV04
Built -In Generation of Functional Broadside Tests Using a Fixed Hardware Structure(IEEE 2015)
15
WSV05
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter(IEEE 2015)
16
WSV06
Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1-1,2n-1,2n}(IEEE 2015)
17
WSV07
Arithmetic-Based Binary-to-RNS Converter Modulo {2n±k} for j n-Bit Dynamic Range(IEEE 2015)
18
WSV08
A Distributed Canny Edge Detector: Algorithm and FPGA Implementation(IEEE 2015)
19
WSV09
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection(IEEE 2015)
20
WSV00
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code(IEEE 2015)
21
WSV01
Single-Port SRAM-Based Transpose Memory with Diagonal Data Mapping for Large Size 2-D DCT/IDCT(IEEE 2015)
22
WSV02
RTL Design and VLSI Implementation of an efficient Convolutional Encoder and Adaptive Viterbi Decoder(IEEE 2013)
23
WSV03
Fast Radix-10 Multiplication Using Redundant BCD Codes(IEEE 2015)
24
WSV04
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block(IEEE 2015)
25
WSV05
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability(IEEE 2015)
26
WSV06
An Optimized Modified Booth Re-coder for Efficient Design of the Add-Multiply Operator(IEEE 2015)
27
WSV07
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations(IEEE 2015)
28
WSV08
High-Performance Hardware Implementation for RC4 Stream Cipher(IEEE 2015)

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