VLSI MINI PROJECT LIST

S.NO
NAME OF MINI PROJECT
01
Design of Free Floating point madness multiplier for Dsp applications. 
02
Design of Sobel edge detector for communication.
03
Design of Delta sigma converter.
04
Design of Phase locked loop using verilog
05
Design of Floating point multiplier and adder /subtractor for multimedia applications. 
06
Design and implementation of Des s-box tables.
07
Design of Reed solemn encoder 
08
Design of Dual port Random access memory.
09
Design of signed integer multiplier
10
Design of unsigned integer multiplier
11
Design of linear feedback shift register used in built in self-test.
12
Design of check sum generator and verifier
13
Design of parity generator and checker.
14
Design of cyclic redundancy checker
15
Design of fast page mode of dynamic random access memory controller
16
Design of static random access memory /read only memory controller
17
Design of hamming code
18
Design of 16 deep ram of 8bit
19
Design of synchronous FIFO
20
Design of direct digital frequency synthesizer.
21
Design of simulation and synthesis of digital FM receiver using vhdl.
22
Design of 8 point fast Fourier transform for processing of multiple signals.
23
Design of A fast base 2 anti-algorithm function  
24
New Adaptive Weight Algorithm for Salt & Pepper Noise Removal.
25
Removal of High Density salt & pepper noise Through Modified Decision Based Un-Symmetric Trimmed Median Filter.
26
Operation improvement of Indoor Robot By gesture Recognition.
27
Adiabatic Technique for Energy Efficient Logic Circuits Design.
28
Enhancing Efficiency In SRAM Array Through Recovery Boosting.
29
Design And FPGA Implementation of Modified Distributive Arithmetic Based DWT-IDWT Processor for Image compression.
30
Enhancing NBIT recovery in SRAM array through recovery boosting.
31
Optimization of processor  architecture for image edge detection filter
32
Design and analysis of TWO low-power  SRAM cell structure
33
A novel column-decoupled 8T cell for low power differential and domino-based SRAM design.
34
CMOS full adder for energy-efficient arithmetic application.
35
Pipelined architecture for FPGA implementation of lifting-based DWT.
36
Parallel architecture for hierarchical optical flow estimation based on FPGA.
37
A  VLSI architecture of SVC encoder for mobile system. 
38
Variability resilient low-power 7T SRAM design for Nano-scaled technologies.
39
Design and implement of the embedded elevator monitor system based on wireless communication.
40
A real time implementation of finger-robot interaction using FPGA.
41
Power estimation of embedded multiplier block in FPGAs
42
Flexible hardware architecture of hierarchical k-means clustering for large cluster number.
43
Keyless car entry through face recognition using FPGA.
44
Image edge detection based on FPGA.
45
Ground bounce noise reduction of low leakage 1-bit nano -cmos based full adder cells for mobile application.
46
Design of a low power flip-flop using cmos deep submicron technology.
47
Low-power and area- efficient carry select adder
48
A pipeline vlsi architecture for high-speed computation of the 1-d discrete wavelet transform.
49
FPGA based inexpensive automobile refuge System.
50
FPGA based inexpensive automobile refuge system
51
Sim card based smart banking using FPGA.
52
New Adaptive Weight Algorithm for Salt & Pepper Noise Removal.
53
Removal of High Density salt & pepper noise Through Modified Decision Based Un-Symmetric Trimmed Median Filter.
54
Operation improvement of Indoor Robot By gesture Recognition.

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