Graduate Diploma Course in VLSI DESIGN


This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts. During this course you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.

Skills Gained:

After completing this course, you will how to:

  • Write RTL Verilog code and Testbench for digital system design
  • Describe the features and benefits of using SystemVerilog
  • Identify the new data types supported in SystemVerilog
  • Utilize an enumerated data type for coding a finite state machine (FSM)
  • Explain how to utilize structures, unions, arrays and oops concepts
  • Describe the new Procedural Statements and Flow Control
  • Define the enhancements and ability to reuse tasks, functions, and packages
  • Identify how to simplify module definitions and instantiations using interfaces….etc


1. Introduction to VLSI

  • VLSI Design Flow
  • ASIC vs FPGA
  • RTL Design Methodologies
  • Introduction to ASIC Verification Methodologies
  • Applications of VLSI

2. Advanced Digital System Design

  • Introduction to Digital Electronics
  • ALU circuits
  • Data processing circuits
  • Universal Logic Elements
  • Combinational circuits – Design and Analysis
  • Latches and Flip Flops
  • Shift Registers and Counters
  • Sequential circuits – Design and Analysis
  • Memories and PLD
  • Finite State Machine


  • Introduction to Verilog
  • Applications of Verilog
  • Verilog language constructs
  • Abstraction levels
  • Data types
  • Verilog operators
  • Declarations - module, ports types
  • Nets and Registers
  • Arrays, Memory modeling
  • FSM –structure, moore vs mealy, coding styles, registered outputs
  • Gate level design
  • Data flow design – assign statements
  • Structural design
  • Behavioral design – procedural statements, always blocks
  • Initial blocks, begin…end, fork…join, blocking and non-blocking
  • Procedural control statements – if, case, loops
  • Tasks, Functions
  • Testbenchs
  • Advanced topics – system tasks, compiler directives, UDP
  • File input and File output


  • Introduction to VHDL
  • Applications of VHDL
  • VHDL language concepts
  • VHDL language basics and constructs
  • Levels of abstraction
  • Data types, Enumerated data types
  • VHDL operators
  • Declarations - libraries, entity, architecture
  • Data Objects - signal, variable, constant
  • Dataflow model - Concurrent assignment statements
  • Structural model - Component declarations
  • Component instantiation
  • Generate Statement, Configuration block
  • Behavioral model - Process statement, Sequential statements
  • Delay concept, Generic concept
  • Arrays, Records, Procedures, Functions
  • Memory modeling
  • FSM –structure, moore vs mealy, coding styles, registered outputs
  • Standard packages, Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Advanced VHDL Topics – assertions, attributes, file handling


  • Basic FPGA Architecture
  • Xilinx Tool Flow.
  • Architecture Wizard and Pins Assignment
  • Reading Reports
  • Global Timing Reports
  • FPGA Design Techniques
  • Synchronous Design Techniques
  • ISIM simulator
  • Synthesis Techniques with Xilinx Synthesis Technology (XST)
  • Implementation Options
  • Core Generator System
  • CORE Generator Software
  • ChipScope-Pro Tool


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VLSI Design projects
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  • Wiztech Automation Solutions Pvt Ltd,
    102, W-Block, 2nd Floor, 2nd Avenue,
    (Next to Indian Bank), Anna Nagar,
    Chennai, Tamil Nadu, India
    Pincode : 600 040.
    Landmark : Anna Nagar Rountana.